//
// Copyright (c) 2004, 2006 Philipp Diethelm
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software, to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to
// do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
// DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
// OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//
//  pci.h
//  Version: 1.1
//
//  Version history
//  1.0  23.01.2006  Initial release
//  1.1  30.01.2006  Changed return type of IsPciBiosPresent() to pcibool
//  1.2  30.01.2006  Added PciSearchForDevice()
//  1.3  31.01.2006  Updated code to uint??_t datatypes
//

#ifndef __PCI_H__INCLUDED__
#define __PCI_H__INCLUDED__

#ifndef __PCI_TYPES_H__INCLUDED__
#include "pcitypes.h"
#endif

//
//  Defines for PCI stuff
//

// Values for GetLastPciError()
#define PCI_ERR_SUCCESS     0x00        // No error (success)
#define PCI_ERR_UNSUPP      0x81        // Unsupported function
#define PCI_ERR_BADVENID    0x83        // Bad vendor id
#define PCI_ERR_NODEV       0x86        // Device not found
#define PCI_ERR_BADREG      0x87        // Bad register number

// Values for BIOS functions
#define PCI_INT             0x1A        // PCI BIOS Interrupt
#define PCI_SIGNATURE       ' ICP'      // Signature for INSTALL call
#define PCI_DEV_MAX         0x1F        // Max. value for dev parameter
#define PCI_FUNC_MAX        0x07        // Max. value for func parameter
#define PCI_BIOS_INSTALL    0xB101      // PCI Bios installation check
#define PCI_BIOS_FINDDEV    0xB102      // PCI Bios find device
#define PCI_BIOS_FINDCLASS  0xB103      // PCI Bios find class
#define PCI_BIOS_CFG_RD8    0xB108      // PCI Bios Read configuration byte
#define PCI_BIOS_CFG_RD16   0xB109      // PCI Bios Read configuration word
#define PCI_BIOS_CFG_RD32   0xB10A      // PCI Bios Read configuration dword
#define PCI_BIOS_CFG_WR8    0xB10B      // PCI Bios Write configuration byte
#define PCI_BIOS_CFG_WR16   0xB10C      // PCI Bios Write configuration word
#define PCI_BIOS_CFG_WR32   0xB10D      // PCI Bios Write configuration dword

// Values for Configuration registers
//  Generic Registers (For all devices)
#define PCI_CFG_R16_VENID   0x00        // Vendor ID register
#define PCI_CFG_R16_DEVID   0x02        // Device ID register
#define PCI_CFG_R16_CMD     0x04        // Command register
#define PCI_CFG_R16_STATUS  0x06        // Status register
#define PCI_CFG_R16_REV     0x08        // Revision ID register
#define PCI_CFG_R24_CLASS   0x09        // Class code
#define PCI_CFG_R8_HDRTYPE  0x0E        // Class code

//  Registers for device with type 0 header
//  There are may more registers, refer to PCI specification
#define PCI_CFG_R32_BAR0    0x10        // BAR0
#define PCI_CFG_R32_BAR1    0x14        // BAR1
#define PCI_CFG_R32_BAR2    0x18        // BAR2
#define PCI_CFG_R32_BAR3    0x1C        // BAR3
#define PCI_CFG_R32_BAR4    0x20        // BAR4
#define PCI_CFG_R32_BAR5    0x24        // BAR5
#define PCI_CFG_R32_CISPTR  0x28        // Cardbus CIS Pointer
#define PCI_CFG_R16_SVID    0x2C        // Subsystem vendor id
#define PCI_CFG_R16_SDID    0x2E        // Subsystem device id
#define PCI_CFG_R32_EXROM   0x30        // Expansion ROM base address
#define PCI_CFG_R8_CAPPTR   0x34        // Capabilities ptr
#define PCI_CFG_R8_INTLINE  0x3C        // Interrupt line
#define PCI_CFG_R8_INTPIN   0x3D        // Interrupt pin

//
//  PCI BIOS generic interfaces
//
uint8_t PciGetLastError();
pcibool IsPciBiosPresent();
uint8_t GetPciBiosVerLo();
uint8_t GetPciBiosVerHi();
uint8_t GetPciBussesInSystem();
uint16_t GetPciDeviceCount();
pcibool PciSearchForDevice(uint16_t venid, uint16_t devid, uint8_t* bus, uint8_t* dev, uint8_t* func, uint16_t* marker);

//
//  PCI configuration registers read access
//
uint8_t PciReadConfigByte(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg);
uint16_t PciReadConfigWord(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg);
uint32_t PciReadConfigDWord(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg);

//
//  PCI configuration registers write access
//
uint8_t PciWriteConfigByte(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint8_t data);
uint8_t PciWriteConfigWord(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint16_t data);
uint8_t PciWriteConfigDWord(uint8_t bus, uint8_t dev, uint8_t func, uint8_t reg, uint32_t data);

#endif
